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2016

MVPA: An FPGA based multi-vector processor architecture

2016 13th International Bhurban Conference on Applied Sciences and Technology (IBCAST)

T. Hussain, O. Palomar, A. Cristal, E. Ayguade, and A. Haider
Access pattern based multi-layer bus virtualization controller

2016 13th International Bhurban Conference on Applied Sciences and Technology (IBCAST)

T. Hussain, O. Palomar, A. Cristal, E. Ayguade, and A. Haider
Task Scheduling Techniques for Asymmetric Multi-core Systems

IEEE Transactions on Parallel and Distributed Systems

K. Chronaki, A. Rico, M. Casas, M. Moreto, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
MUSA: A Multi-level Simulation Approach for Next-generation HPC Machines

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

T. Grass, C. Allande, A. Armejach, A. Rico, E. Ayguade, J. Labarta, M. Valero, M. Casas, and M. Moreto
Analyzing the effect of last level cache sharing on integrated platforms with fine-grain CPU-GPU collaboration

GPU Technology Conference Euope (GTC Europe)

V. Garcia, J. Gomez-Luna, T. Grass, A. Rico, A. J. Pena, and E. Ayguade
Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications

Workload Characterization (IISWC), 2016 IEEE International Symposium on

V. Garcia, J. Gomez-Luna, T. Grass, A. Rico, E. Ayguade, and A. J. Pena
AXIOM: A Hardware-Software Platform for Cyber Physical Systems

2016 Euromicro Conference on Digital System Design (DSD)

S. Mazumdar, E. Ayguade, N. Bettin, J. Bueno, S. Ermini, A. Filgueras, D. Jiménez-González, C. Alvarez Martinez, X. Martorell, F. Montefoschi, D. Oro, D. Pnevmatikatos, A. Rizzo, D. Theodoropoulos, and R. Giorgi
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

K. Chronaki, M. Moreto, M. Casas, A. Rico, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
Multiple Target Task Sharing Support for the OpenMP Accelerator Model

OpenMP: Memory, Devices, and Tasks. 12th International Workshop on OpenMP, IWOMP 2016, Nara, Japan, October 5-7, 2016, Proceedings

G. Ozen, S. Mateo, E. Ayguade, J. Labarta, and J. Beyer
The Secrets of the Accelerators Unveiled: Tracing Heterogeneous Executions Through OMPT

OpenMP: Memory, Devices, and Tasks. 12th International Workshop on OpenMP, IWOMP 2016, Nara, Japan, October 5-7, 2016, Proceedings

G. Llort, A. Filgueras, D. Jiménez-González, H. Servat, X. Teruel, E. Mercadal, C. Álvarez, J. Giménez, X. Martorell, E. Ayguade, and J. Labarta

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